![Machine language monitor running on a [[W65C816S](https://upload.wikimedia.org/wikipedia/commons/c/c0/W65C816S_Machine_Code_Monitor.jpeg) 마이크로프로세서, 코드 디스어셈블리와 프로세서 레지스터 및 메모리 덤프를 표시하고 있다]]

Machine code

{{Short description |Instructions directly executable by a computer}} {{for|code that is completely internal to some CPUs and normally inaccessible to programmers|Microcode}} {{redirect|Native code|the French colonial legal system|Native code (France)}} {{use dmy dates|date=December 2021|cs1-dates=y}} {{use list-defined references|date=December 2021}} [[File:W65C816S Machine Code Monitor.jpeg|thumb|upright=1.35|Machine language monitor running on a [[W65C816S]] [[microprocessor]], displaying [[disassembler|code disassembly]] and [[Core dump|dumps]] of processor register and memory]] {{Program execution}}

In [[computing]], '''machine code''' is [[data]] [[encoded]] and structured to control a [[computer]]'s [[central processing unit]] (CPU) via its programmable [[Interface (computing)|interface]]. A [[computer program]] consists primarily of sequences of machine-code instructions. Machine code is classified as [[native (computing)|native]] with respect to its host CPU since it is the language that the CPU interprets directly. Some [[interpreter (computing)|software interpreters]] translate the [[programming language]] that they interpret into a virtual machine code ([[bytecode]]) and process it with a [[P-code machine]].

A machine-code instruction causes the CPU to perform a specific task such as:

Load a [[Word (computer architecture)|word]] from [[Random-access memory|memory]] to a [[Processor register|CPU register]]
Execute an [[arithmetic logic unit]] (ALU) operation on one or more registers or memory locations
[[jump instruction|Jump]] or [[Addressing mode#Skip|skip]] to an instruction that is not the next one

An [[instruction set architecture]] (ISA) defines the interface to a CPU and varies by groupings or families of CPU design such as [[x86]] and [[ARM architecture family |ARM]]. Generally, machine code compatible with one family is not with others, but there are exceptions. The [[VAX]] architecture includes optional support of the [[PDP-11]] instruction set. The [[IA-64]] architecture includes optional support of the [[IA-32]] instruction set. And, the [[PowerPC 600#PowerPC 615|PowerPC 615]] can natively process both [[PowerPC]] and x86 instructions.

==Assembly language== [[File:Machine language and assembly language.jpg|thumb|319x319px|Translation of assembly into machine code]]

[[Assembly language]] provides a relatively direct mapping from a [[human-readable]] [[source code]] to machine code. The assembly language source code represents numerical codes in machine code, as mnemonics and labels. For example, [[NOP (code)|NOP]] in assembly for an [[x86]] processor represents the x86 architecture [[opcode]] 0x90 in machine code. While it is possible to write a program in machine code, doing so is tedious and error-prone. Therefore, programs are usually written in assembly or, more commonly, in a [[high-level programming language]].

==Instruction set== A machine instruction encodes an operation as a pattern of [[bit]]s based on the specified format for the machine's instruction set.On early [[Decimal computer|decimal machines]], patterns of characters, digits and digit sign{{harvnb|Tanenbaum|1990|p= [https://archive.org/details/structuredcomput00tane/page/251 251]}}

Instruction sets differ in various ways. Instructions of a set might all be the same length or different instructions might have different lengths; they might be smaller than, the same size as, or larger than the [[Word (computer architecture)|word]] size of the architecture. The number of instructions may be relatively small or large. Instructions may or may not have to be aligned on particular memory boundaries, such as the architecture's word boundary.

An instruction set needs to execute the circuits of a computer's [[Logic level|digital logic level]]. At the digital level, the program needs to control the computer's registers, bus, memory, ALU, and other hardware components.{{harvnb|Tanenbaum|1990|p= [https://archive.org/details/structuredcomput00tane/page/162 162]}} To control a computer's [[Computer architecture|architectural]] features, machine instructions are created. Examples of features that are controlled using machine instructions:

[[memory segmentation|segment registers]]{{harvnb|Tanenbaum|1990|p= [https://archive.org/details/structuredcomput00tane/page/231 231]}}
[[protected mode|protected address mode]]{{harvnb|Tanenbaum|1990|p= [https://archive.org/details/structuredcomput00tane/page/237 237]}}
[[binary-coded decimal]] (BCD) arithmetic{{harvnb|Tanenbaum|1990|p= [https://archive.org/details/structuredcomput00tane/page/236 236]}}

The criteria for instruction formats include:

Instructions most commonly used should be shorter than instructions rarely used.
The [[High Bandwidth Memory|memory transfer rate]] of the underlying hardware determines the flexibility of the memory fetch instructions.
The number of bits in the [[Random-access_memory#Addressing|address field]] requires special consideration.{{harvnb|Tanenbaum|1990|p= [https://archive.org/details/structuredcomput00tane/page/253 253]}}

Determining the size of the address field is a choice between space and speed. On some computers, the number of bits in the address field may be too small to access all of the physical memory. Also, [[virtual address space]] needs to be considered. Another constraint may be a limitation on the size of registers used to construct the address. Whereas a shorter address field allows the instructions to execute more quickly, other physical properties need to be considered when designing the instruction format.

Instructions can be separated into two types: general-purpose and special-purpose. Special-purpose instructions exploit architectural features that are unique to a computer. General-purpose instructions control architectural features common to all computers.{{harvnb|Tanenbaum|1990|p= [https://archive.org/details/structuredcomput00tane/page/283 283]}}

General-purpose instructions control:

Data movement from one place to another
Monadic operations that have one [[operand]] to produce a result
Dyadic operations that have two operands to produce a result
Comparisons and conditional jumps
Procedure calls
Loop control
Input/output

==={{anchor |Overlapping instructions}}Overlapping instruction=== On processor architectures with [[variable-length instruction set]]s (such as [[Intel]]'s [[x86]] processor family) it is, within the limits of the control-flow [[self-synchronizing code|resynchronizing]] phenomenon known as the [[Kruskal count]], sometimes possible through opcode-level programming to deliberately arrange the resulting code so that two code paths share a common fragment of opcode sequences. These are called ''overlapping instructions'', ''overlapping opcodes'', ''overlapping code'', ''overlapped code'', ''instruction scission'', or ''jump into the middle of an instruction''.

In the 1970s and 1980s, overlapping instructions were sometimes used to preserve memory space. One example was in the implementation of error tables in [[Microsoft]]'s [[Altair BASIC]], where ''interleaved instructions'' mutually shared their instruction bytes. The technique is rarely used today, but might still be necessary to resort to in areas where extreme optimization for size is necessary on the byte level such as in the implementation of [[boot loader]]s which have to fit into [[boot sector]]s.

It is also sometimes used as a [[code obfuscation]] technique as a measure against [[disassembly]] and tampering.

The principle is also used in shared code sequences of [[fat binaries]] which must run on multiple instruction-set-incompatible processor platforms.

This property is also used to find [[unintended instruction]]s called [[gadget (machine instruction sequence)|gadget]]s in existing code repositories and is used in [[return-oriented programming]] as alternative to [[code injection]] for exploits such as [[return-to-libc attack]]s.

===Microcode=== In some computers, the machine code of the [[computer architecture |architecture]] is implemented by an even more fundamental underlying layer called [[microcode]], providing a common machine language interface across a line or family of different models of computer with widely different underlying [[dataflow]]s. This is done to facilitate [[porting]] of machine language programs between different models.{{Cite book |last1=Kent |first1=Allen |url=https://books.google.com/books?id=EjWV8J8CQEYC&pg=PA33 |title=Encyclopedia of Computer Science and Technology: Volume 28 - Supplement 13: AerosPate Applications of Artificial Intelligence to Tree Structures |last2=Williams |first2=James G. |date=1993-04-05 |publisher=CRC Press |isbn=978-0-8247-2281-4 |pages=33–34 |language=en}} An example of this use is the IBM [[System/360]] family of computers and their successors.{{Cite journal |last=Tucker |first=S. G. |date=31 December 1967 |title=Microprogram control for SYSTEM/360 |url=https://ieeexplore.ieee.org/document/5388391 |journal=IBM Systems Journal |volume=6 |issue=4 |pages=222–241 |doi=10.1147/sj.64.0222 |issn=0018-8670 |via=IEEE Xplore|url-access=subscription }}

==Examples== ===IBM 709x=== The [[IBM 700/7000 series#Later scientific architecture (704/709/7090/7094)|IBM 704, 709, 704x and 709x]] store one instruction in each instruction word; IBM numbers the bit from the left as S, 1, ..., 35. Most instructions have one of two formats:

;Generic :S,1-11 :12-13 Flag, ignored in some instructions :14-17 unused :18-20 Tag :21-35 Y

;Index register control, other than TSX :S,1-2 Opcode :3-17 Decrement :18-20 Tag :21-35 Y

For all but the [[IBM 7094]] and 7094 II, there are three index registers designated A, B and C; indexing with multiple 1 bits in the tag subtracts the [[logical or]] of the selected index registers and loading with multiple 1 bits in the tag loads all of the selected index registers. The 7094 and 7094 II have seven index registers, but when they are powered on they are in ''multiple tag mode'', in which they use only the three of the index registers in a fashion compatible with earlier machines, and require a Leave Multiple Tag Mode ('''LMTM''') instruction in order to access the other four index registers.

The effective address is normally Y-C(T), where C(T) is either 0 for a tag of 0, the logical or of the selected index registers in multiple tag mode or the selected index register if not in multiple tag mode. However, the effective address for index register control instructions is just Y.

A flag with both bits 1 selects indirect addressing; the indirect address word has both a tag and a Y field.

In addition to ''transfer'' (branch) instructions, these machines have skip instruction that conditionally skip one or two words, e.g., Compare Accumulator with Storage (CAS) does a three way compare and conditionally skips to NSI, NSI+1 or NSI+2, depending on the result.

===MIPS=== The [[MIPS architecture]] provides a specific example for a machine code whose instructions are always 32 bits long.{{Rp|299}} The general type of instruction is given by the ''op'' (operation) field, the highest 6 bits. J-type (jump) and I-type (immediate) instructions are fully specified by ''op''. R-type (register) instructions include an additional ''funct'' (function) field to determine the exact operation. The fields used in these types are:

6      5     5     5     5      6 bits

[ op | rs | rt | rd |shamt| funct] R-type [ op | rs | rt | address/immediate] I-type [ op | target address ] J-type

''rs'', ''rt'', and ''rd'' indicate register operands; ''shamt'' gives a shift amount; and the ''address'' or ''immediate'' fields contain an operand directly.{{Rp|299–301}}

For example, adding the registers 1 and 2 and placing the result in register 6 is encoded:{{Rp|554}}

[ op | rs | rt | rd |shamt| funct] 0 1 2 6 0 32 decimal 000000 00001 00010 00110 00000 100000 binary

Load a value into register 8, taken from the memory cell 68 cells after the location listed in register 3:{{Rp|552}}

[ op | rs | rt | address/immediate] 35 3 8 68 decimal 100011 00011 01000 00000 00001 000100 binary

Jumping to the address 1024:{{Rp|552}}

[ op | target address ] 2 1024 decimal 000010 00000 00000 00000 10000 000000 binary

==Bytecode== Machine code is similar to yet fundamentally different from [[bytecode]]. Like machine code, bytecode is typically generated (i.e. by a compiler) from source code. But, unlike machine code, bytecode is not directly executable by a CPU. An exception is if a processor is designed to use bytecode as its machine code, such as the [[Java processor]]. If bytecode is processed by an software interpreter, then that interpreter is a [[virtual machine]] for which the bytecode is its machine code.

==Storage== During execution, machine code is generally stored in RAM although running from ROM is supported by some devices. Regardless, the code may also be cached in more specialized memory to enhance performance. There may be different caches for instructions and data, depending on the architecture.{{Cite journal |last1=Su |first1=Chao |last2=Zeng |first2=Qingkai |date=2021 |title=Survey of CPU Cache-Based Side-Channel Attacks: Systematic Analysis, Security Models, and Countermeasures |journal=Security and Communication Networks |language=en |volume=2021 |issue=1 |article-number=5559552 |doi=10.1155/2021/5559552 |doi-access=free |issn=1939-0122}}

From the point of view of a [[process (computing)|process]], the machine code lives in ''code space'', a designated part of its [[virtual address space |address space]]. In a [[Thread (computing)|multi-threading]] environment, different threads of one process share code space along with data space, which reduces the overhead of [[context switching]] considerably as compared to process switching.{{Cite web |title=CS 537 Notes, Section #3A: Processes and Threads |url=https://pages.cs.wisc.edu/~bart/537/lecturenotes/processes-threads.html |access-date=2025-07-18 |website=pages.cs.wisc.edu |publisher=School of Computer, Data & Information Sciences, University of Wisconsin-Madison}}

==Readability== Machine code is generally considered to be not human readable,{{Sfn|Samuelson|1984|p=683}} with [[Douglas Hofstadter]] comparing it to examining the atoms of a [[DNA]] molecule.{{Sfn|Hofstadter|1979|p=[https://archive.org/details/godelescherbach00doug/page/290 290]}} However, various tools and methods support understanding machine code.

[[Disassembly]] decodes machine code to assembly language which is possible since assembly instructions can often be mapped one-to-one to machine instructions.{{Sfn|Tanenbaum|1990|p=[https://archive.org/details/structuredcomput00tane/page/398 398]}}

A [[decompiler]] converts machine code to a [[High-level programming language |high-level language]], but the result can be relatively [[Obfuscation (software)|obfuscated]] (hard to understand).

A program can be associated with [[debug symbol]]s (either embedded in the [[executable#native executable|native executable]] or in a separate file) that allow it to be mapped to external source code. A [[debugger]] reads the symbols to help a programmer interactively [[debugging |debug]] the program. Examples include:

The [[SHARE Operating System]] (1959) for the [[IBM 709]], [[IBM 7090]], and [[IBM 7094]] computers allowed for an loadable code format named [[SQUOZE]]. SQUOZE was a compressed binary form of [[assembly language]] code and included a symbol table.
Modern IBM mainframe [[operating system]]s, such as [[z/OS]], have available a symbol table named ''Associated data'' (ADATA). The table is stored in a file that can be produced by the [[IBM High-Level Assembler]] (HLASM), IBM's [[COBOL]] compiler, and IBM's [[PL/I]] compiler,{{cite web |date=2025-03-17 |title=SYSADATA message information |url=https://www.ibm.com/docs/en/epfz/6.1?topic=guide-sysadata-message-information |work=Enterprise PL/I for z/OS 6.1 information |language=en-US}} either as a separate SYSADATA file or as ADATA records in a [[Generalized object output file]] (GOFF). This obsoletes the TEST records from [[OS/360]], although it is still possible to request them and to use them in the [[Time Sharing Option|TSO]] TEST command.
[[Windows]] uses a symbol table that is stored in a [[program database]] ({{mono|.pdb}}) file.
Most [[Unix-like]] operating systems have available symbol table formats named [[stabs]] and [[DWARF]]. In [[macOS]] and other [[Darwin (operating system)|Darwin]]-based operating systems, the debug symbols are stored in DWARF format in a separate {{mono|.dSYM}} file.

==See also== {{Wiktionary|machine code}}

{{Annotated link |Endianness}}
{{Annotated link |List of programming languages by type#Machine languages|List of machine languages}}
{{Annotated link |Machine code monitor}}
{{Annotated link |Micro-Professor MPF-I}}
{{Annotated link |Executable#native executable|native executable}}
{{Annotated link |Object code}}
{{Annotated link |P-code machine}}
{{Annotated link |Reduced instruction set computer}} (RISC)
{{Annotated link |Very long instruction word}}

==Notes== {{reflist|group="nb"|refs= For example, the [[DR-DOS]] [[master boot record]]s (MBRs) and [[volume boot record|boot sectors]] (which also hold the [[partition table]] and [[BIOS Parameter Block]], leaving less than 446 respectively 423 bytes for the code) were traditionally able to locate the boot file in the [[FAT12]] or [[FAT16]] [[file system]] by themselves and load it into memory as a whole, in contrast to their counterparts in [[MS-DOS]] and [[PC DOS]], which instead rely on the [[system file]]s to occupy the first two [[directory entry]] locations in the file system and the first three sectors of [[IBMBIO.COM]] to be stored at the start of the data area in contiguous sectors containing a secondary loader to load the remainder of the file into memory (requiring [[SYS (DOS command)|SYS]] to take care of all these conditions). When [[FAT32]] and [[logical block addressing]] (LBA) support was added, [[Microsoft]] even switched to require [[i386]] instructions and split the boot code over two sectors for code size reasons, which was no option to follow for DR-DOS as it would have broken [[Backward compatibility|backward]]- and cross-compatibility with other operating systems in [[multi-boot]] and [[chain load]] scenarios, and as with older [[IBM PC–compatible]] PCs. Instead, the [[DR-DOS 7.07]] boot sectors resorted to [[self-modifying code]], [[opcode]]-level programming in machine language, controlled utilization of (documented) [[side effect (computer science)|side effect]]s, multi-level data/code overlapping and algorithmic [[Fold (higher-order function)|folding]] techniques to still fit everything into a physical sector of only 512 bytes without giving up any of their extended functions. While overlapping instructions on processor architectures with [[variable-length instruction set]]s can sometimes be arranged to merge different code paths back into one through control-flow [[self-synchronizing code|resynchronization]], overlapping code for different processor architectures can sometimes also be crafted to cause execution paths to branch into different directions depending on the underlying processor, as is sometimes used in [[fat binaries]]. }}

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==Sources==

{{cite book |last=Hofstadter |first=Douglas R. |author-link=Douglas Hofstadter |date=1979 |url=https://archive.org/details/godelescherbach00doug |url-access=registration |title=Gödel, Escher, Bach: An Eternal Golden Braid |publisher=[[Basic Books]] |isbn=0-465-02685-0 |access-date=2025-02-10}}
{{cite journal |last=Samuelson |first=Pamela |author-link=Pamela Samuelson |date=1984 |url=https://scholarship.law.duke.edu/dlj/vol33/iss4/2 |title=CONTU Revisited: The Case Against Copyright Protection for Computer Programs in Machine-Readable Form |journal=[[Duke Law Journal]] |volume=33 |issue=4 |pages=663–769 |doi=10.2307/1372418 |jstor=1372418 |hdl=hein.journals/duklr1984 |access-date=2025-02-10|url-access=subscription }}
{{cite book | last = Tanenbaum | first = Andrew S. | author-link = Andrew S. Tanenbaum | title = Structured Computer Organization, Third Edition | publisher = Prentice Hall | year = 1990 | page = [https://archive.org/details/structuredcomput00tane/page/398 398] | isbn = 978-0-13-854662-5 | url = https://archive.org/details/structuredcomput00tane/page/398 }}

==Further reading==

{{cite book |last1=Hennessy |first1=John L. |author1-link=John L. Hennessy |last2=Patterson |first2=David A. |author2-link=David A. Patterson (scientist) |date=1994 |title=Computer Organization and Design. The Hardware/Software Interface. |publisher=[[Morgan Kaufmann Publishers]] |isbn=1-55860-281-X |url-access=registration |url=https://archive.org/details/computerorganiza00henn}}
{{cite book |last1=Tanenbaum |first1=Andrew S. |author1-link=Andrew S. Tanenbaum |date=1999 |url=https://archive.org/details/structuredcomput0000tane_x7x6 |url-access=registration |title=Structured Computer Organization |edition=Fourth |publisher=[[Prentice Hall]] |isbn=0-13-020435-8 |access-date=2025-02-10}}
{{cite book |last1=Brookshear |first1=J. Glenn |date=2007 |url=https://archive.org/details/computerscienceo0000broo_e5b8 |url-access=registration |title=Computer Science: An Overview |edition=Ninth |publisher=[[Addison Wesley]] |isbn=978-0-321-38701-1 |access-date=2025-02-10}}

[[Category:Machine code| ]] [[Category:Assembly languages|*]] [[Category:Low-level programming languages]]